A DV Approach to Post-Silicon: Validating SoC Low Power through Synthetic Software Scenarios

Lightweight execution environments like the Little Kernel (LK) are commonly deployed in post-silicon validation to assess software-hardware interactions. These bare-metal kernels, however, lack the sophisticated power management features present in full operating systems, such as the Generic Power Domain (GenPD) framework. Instead of building complex software abstractions that simulate production-grade power management drivers, this paper applies a Design Verification (DV) approach to post silicon. By discarding standard software paradigms, the introduced framework leverages fundamental bare-metal kernel primitives to intentionally engineer synthetic, non-deterministic stressors. Eliminating intermediate software layers allows us to utilize the bare-metal setup to drive chaotic, aggressive stimuli straight to the hardware execution layer.

• Hardware and Architecture