Abstract
Silent performance degradation and accelerator contention remain largely unaddressed in contemporary heterogeneous training systems, where Field-Programmable Gate Array (FPGA) offloading decisions are often static, heuristic-driven, or evaluated using idealized assumptions that ignore queueing effects, transfer overheads, and shared accelerator load. This paper introduces a runtime, price-conscious co-execution integration of CPU and FPGA to train deep learning models, where execution choices are dynamically made at the training stage granularity with a discrete latency cost model. The proposed method incorporates the CPU execution latency estimation, FPGA queue depth monitoring, time-varying service rate modeling, background contention, data transfer overhead, and switching hysteresis into a single decision mechanism that is driven by an ARM-based runtime monitor. The model is realistic FPGA queueing model, which is used to simulate shared accelerator contention and avoid optimistic assumptions of performance. Experimental evaluation on a representative convolutional training pipeline demonstrates that the cost-minimizing orchestration case achieves a mean training step time of 0.0213 s (±0.0036) with a throughput proxy of 47.03 steps/s, while maintaining bounded FPGA queue behavior and 99.94% stall avoidance relative to static FPGA execution. Conversely, a different execution setup that has a greater FPGA usage shows a greater queue buildup, an average step time of 0.0330 s, a maximum FPGA queue depth of 77 units, and a high level of congestion exposure, which demonstrates how crucial a queue-aware execution configuration is. These findings underscore the fact that the acceleration capability of the FPGA is not controlled by the raw compute capability but it is controlled by runtime sensitive and contention-sensitive orchestration, creating a principled and reproducible methodology to evaluate heterogeneous training systems in realistic conditions of accelerator sharing.