Physical Design Aware Verification Methodology for Closing Coverage Gaps in SharedBus MBIST

The industry shift toward SharedBus MBIST architectures has successfully mitigated the Power, Performance, and Area (PPA) bottlenecks associated with traditional embedded memory testing. However, reusing functional paths for testing introduces severe verification challenges, as conventional MBIST algorithms often fail to detect intricate mapping errors like data-bus scrambling, tiedoff data bits, and irregular address bits decoding. If left undetected, these discrepancies in implementation result in silent coverage gaps and ineffective memory repair mechanisms. This paper proposes a robust assertion-based RTL verification methodology specifically designed to close these gaps in SharedBus MBIST implementations. By deploying a Walking-0 pattern and continuous monitors across SharedBus and physical memory interfaces, the methodology enforces a strict set of verification rules. Experimental results validate this approach, demonstrating the successful identification of critical implementation bugs across multiple vendor cores that escaped conventional verification. The paper concludes by proving that the overhead of this methodology is minimal and highly justified by the resulting improvements in silicon quality.

• Hardware and Architecture