Kavya Sreedhar
Kavya Sreedhar is a research scientist at Google, working on hardware/software co-design for TPUs. In August 2024, she defended her PhD in electrical engineering at Stanford, advised by Mark Horowitz. She received a M.S. in electrical engineering from Stanford in 2020 and a B.S. in electrical engineering and a B.S. in business, economics, and management from Caltech in 2019. Her graduate school research was supported by Stanford's Knight-Hennessy Graduate Fellowship (2019 to 2022) and the Quad Fellowship (2023 to 2024). During the summer, she has interned with Meta Silicon Research, NVIDIA's Architecture Research Group, Apple, Microsoft, and Intel. Her website is at bit.ly/kavyasreedhar.
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Modeling multi-chiplet architectures for TPU co-design
Pritha Doddahosahally Narayanappa
Hung-Ming Hsu
Khai Tran
Hardie Cate
Narges Shahidi
Zhijie Deng
Avinash Lingamneni
Thejasvi Vijayaraj
Aditya Yanamandra
Sameer Kumar
Ming Liu
Lluis-Miquel Munguia
2026
Preview abstract
We present an experience report on modeling multi-chiplet hardware accelerators for TPU co-design, and argue that detailed chiplet modeling is necessary to identify bottlenecks and optimizations for future hardware design. Our chiplet modeling tool (CMT) shows that at lower target serving latencies, serving queries/second/chip (QPS/chip) can be up to $2.2\times$ different with chiplet modeling compared to modeling with aggregated compute and memory resources. With this tool, we identify interdependencies between chiplet modeling and the rest of the system: we highlight an example where cost savings from prefetching weights from HBM to local SRAM need to be incorporated in the selection heuristic for chiplet sharding strategies. Using CMT, we explore performance sensitivity to chiplet properties in a design space exploration that highlights considerations for high-performance serving. We use an open-source MoE model (OSS-MoE) served on Ironwood-like TPU architectures as a case study. We conclude by discussing the need to establish best sharding practices to narrow this large design search space.
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